2013-10-08 15:07:03 +08:00
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/* descriptor.h
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2015-01-31 22:00:00 +08:00
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Copyright (c) 2015, Nikolaj Schlej. All rights reserved.
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2013-10-08 15:07:03 +08:00
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHWARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*/
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#ifndef __DESCRIPTOR_H__
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#define __DESCRIPTOR_H__
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2013-11-07 21:46:28 +08:00
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#include <QString>
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2013-10-08 15:07:03 +08:00
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#include "basetypes.h"
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// Make sure we use right packing rules
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2015-09-07 05:46:26 +08:00
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#pragma pack(push, 1)
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2013-10-08 15:07:03 +08:00
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// Flash descriptor header
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typedef struct _FLASH_DESCRIPTOR_HEADER {
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UINT8 FfVector[16]; // Must be 16 0xFFs
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UINT32 Signature; // 0x0FF0A55A
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} FLASH_DESCRIPTOR_HEADER;
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// Flash descriptor signature
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#define FLASH_DESCRIPTOR_SIGNATURE 0x0FF0A55A
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// Descriptor region size
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#define FLASH_DESCRIPTOR_SIZE 0x1000
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// Descriptor map
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// Base fields are storing bits [11:4] of actual base addresses, all other bits are 0
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typedef struct _FLASH_DESCRIPTOR_MAP {
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// FLMAP0
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UINT32 ComponentBase : 8;
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UINT32 NumberOfFlashChips : 2; // Zero-based number of flash chips installed on board
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UINT32 : 6;
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UINT32 RegionBase : 8;
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UINT32 : 8;
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// FLMAP 1
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UINT32 MasterBase : 8;
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UINT32 NumberOfMasters : 2;
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UINT32 : 6;
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UINT32 PchStrapsBase : 8;
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UINT32 NumberOfPchStraps : 8; // One-based number of UINT32s to read as PCH straps, min=0, max=255 (1 Kb)
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// FLMAP 2
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UINT32 ProcStrapsBase : 8;
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UINT32 NumberOfProcStraps : 8; // One-based number of UINT32s to read as processor straps, min=0, max=255 (1 Kb)
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UINT32: 16;
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} FLASH_DESCRIPTOR_MAP;
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// Component section
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2014-07-25 07:59:51 +08:00
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// Flash parameters DWORD structure
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typedef struct _FLASH_PARAMETERS {
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UINT8 FirstChipDensity : 4;
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UINT8 SecondChipDensity : 4;
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UINT8 : 8;
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UINT8 : 1;
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UINT8 ReadClockFreqency : 3; // Hardcoded value of 20 Mhz (000b) in v1 descriptors and 17 Mhz (110b) in v2 ones
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UINT8 FastReadEnabled : 1;
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UINT8 FastReadFreqency : 3;
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UINT8 FlashReadStatusFrequency : 3;
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UINT8 FlashWriteFrequency : 3;
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UINT8 DualOutputFastReadSupported : 1;
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UINT8 : 1;
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} FLASH_PARAMETERS;
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// Flash densities
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#define FLASH_DENSITY_512KB 0x00
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#define FLASH_DENSITY_1MB 0x01
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#define FLASH_DENSITY_2MB 0x02
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#define FLASH_DENSITY_4MB 0x03
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#define FLASH_DENSITY_8MB 0x04
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#define FLASH_DENSITY_16MB 0x05
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#define FLASH_DENSITY_32MB 0x06
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#define FLASH_DENSITY_64MB 0x07
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#define FLASH_DENSITY_UNUSED 0x0F
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2014-02-02 20:26:33 +08:00
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// Flash frequencies
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#define FLASH_FREQUENCY_20MHZ 0x00
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#define FLASH_FREQUENCY_33MHZ 0x01
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#define FLASH_FREQUENCY_48MHZ 0x02
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#define FLASH_FREQUENCY_50MHZ_30MHZ 0x04
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#define FLASH_FREQUENCY_17MHZ 0x06
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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FLASH_PARAMETERS FlashParameters;
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UINT8 InvalidInstruction0; // Instructions for SPI chip, that must not be executed, like FLASH ERASE
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UINT8 InvalidInstruction1; //
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UINT8 InvalidInstruction2; //
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UINT8 InvalidInstruction3; //
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} FLASH_DESCRIPTOR_COMPONENT_SECTION;
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2015-09-07 05:46:26 +08:00
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION_V2 {
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FLASH_PARAMETERS FlashParameters;
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UINT8 InvalidInstruction0; // Instructions for SPI chip, that must not be executed, like FLASH ERASE
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UINT8 InvalidInstruction1; //
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UINT8 InvalidInstruction2; //
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UINT8 InvalidInstruction3; //
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UINT8 InvalidInstruction4; //
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UINT8 InvalidInstruction5; //
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UINT8 InvalidInstruction6; //
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UINT8 InvalidInstruction7; //
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} FLASH_DESCRIPTOR_COMPONENT_SECTION_V2;
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2013-10-08 15:07:03 +08:00
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// Region section
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// All base and limit register are storing upper part of actual UINT32 base and limit
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// If limit is zero - region is not present
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typedef struct _FLASH_DESCRIPTOR_REGION_SECTION {
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UINT16 :16;
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UINT16 FlashBlockEraseSize; // Size of block erased by single BLOCK ERASE command
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UINT16 Region0Base; // BIOS
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UINT16 Region0Limit; //
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UINT16 Region1Base; // ME
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UINT16 Region1Limit; //
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UINT16 Region2Base; // GbE
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UINT16 Region2Limit; //
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UINT16 Region3Base; // PDR
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UINT16 Region3Limit; //
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UINT16 Region4Base; // Reserved region
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UINT16 Region4Limit; //
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UINT16 Region5Base; // Reserved region
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UINT16 Region5Limit; //
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UINT16 Region6Base; // Reserved region
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UINT16 Region6Limit; //
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UINT16 Region7Base; // Reserved region
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UINT16 Region7Limit; //
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UINT16 Region8Base; // EC
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UINT16 Region8Limit; //
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} FLASH_DESCRIPTOR_REGION_SECTION;
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// Flash block erase sizes
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#define FLASH_BLOCK_ERASE_SIZE_4KB 0x0000
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#define FLASH_BLOCK_ERASE_SIZE_8KB 0x0001
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#define FLASH_BLOCK_ERASE_SIZE_64KB 0x000F
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// Master section
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION {
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UINT16 BiosId;
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UINT8 BiosRead;
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UINT8 BiosWrite;
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UINT16 MeId;
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UINT8 MeRead;
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UINT8 MeWrite;
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UINT16 GbeId;
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UINT8 GbeRead;
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UINT8 GbeWrite;
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} FLASH_DESCRIPTOR_MASTER_SECTION;
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2015-09-07 05:46:26 +08:00
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// Master section v2 (Skylake+)
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION_V2 {
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UINT32 : 8;
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UINT32 BiosRead : 12;
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UINT32 BiosWrite : 12;
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UINT32 : 8;
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UINT32 MeRead : 12;
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UINT32 MeWrite : 12;
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UINT32 : 8;
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UINT32 GbeRead : 12;
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UINT32 GbeWrite : 12;
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UINT32 :32;
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UINT32 : 8;
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UINT32 EcRead : 12;
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UINT32 EcWrite : 12;
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} FLASH_DESCRIPTOR_MASTER_SECTION_V2;
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2014-01-28 21:48:04 +08:00
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// Region access bits in master section
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#define FLASH_DESCRIPTOR_REGION_ACCESS_DESC 0x01
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#define FLASH_DESCRIPTOR_REGION_ACCESS_BIOS 0x02
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#define FLASH_DESCRIPTOR_REGION_ACCESS_ME 0x04
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#define FLASH_DESCRIPTOR_REGION_ACCESS_GBE 0x08
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#define FLASH_DESCRIPTOR_REGION_ACCESS_PDR 0x10
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#define FLASH_DESCRIPTOR_REGION_ACCESS_EC 0x20
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// Base address of descriptor upper map
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#define FLASH_DESCRIPTOR_UPPER_MAP_BASE 0x0EFC
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// Descriptor upper map structure
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typedef struct _FLASH_DESCRIPTOR_UPPER_MAP {
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UINT8 VsccTableBase; // Base address of VSCC Table for ME, bits [11:4]
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UINT8 VsccTableSize; // Counted in UINT32s
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UINT16 ReservedZero; // Still unknown, zero in all descriptors I have seen
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} FLASH_DESCRIPTOR_UPPER_MAP;
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// VSCC table entry structure
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typedef struct _VSCC_TABLE_ENTRY {
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UINT8 VendorId; // JEDEC VendorID byte
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UINT8 DeviceId0; // JEDEC DeviceID first byte
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UINT8 DeviceId1; // JEDEC DeviceID second byte
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UINT8 ReservedZero; // Reserved, must be zero
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UINT32 VsccRegisterValue; // VSCC register value
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} VSCC_TABLE_ENTRY;
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// Base address and size of OEM section
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#define FLASH_DESCRIPTOR_OEM_SECTION_BASE 0x0F00
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#define FLASH_DESCRIPTOR_OEM_SECTION_SIZE 0xFF
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// Restore previous packing rules
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#pragma pack(pop)
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// Calculate address of data structure addressed by descriptor address format
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// 8 bit base or limit
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extern const UINT8* calculateAddress8(const UINT8* baseAddress, const UINT8 baseOrLimit);
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// 16 bit base or limit
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extern const UINT8* calculateAddress16(const UINT8* baseAddress, const UINT16 baseOrLimit);
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2013-10-15 23:19:15 +08:00
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2013-11-20 09:19:48 +08:00
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// Calculate offset of region using it's base
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extern UINT32 calculateRegionOffset(const UINT16 base);
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2013-11-20 09:19:48 +08:00
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// Calculate size of region using it's base and limit
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2013-10-09 08:53:39 +08:00
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extern UINT32 calculateRegionSize(const UINT16 base, const UINT16 limit);
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2014-01-11 17:20:58 +08:00
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#endif
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