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https://github.com/LongSoft/UEFITool.git
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UT 0.21.0
- added support for new Intel descriptor type, based on [this](http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1f7fd720c81755144423f2d4062c39cc651adc0a) coreboot commit, thanks to lordkag for issue #32 - solved a bug with incorrect volume free space item placement during volume replace, now works as expected - solved an issue with incorrect Aptio capsule parsing introduced in 0.20.8
This commit is contained in:
Nikolaj Schlej
parent
9c4ddbec62
commit
aa80837bf5
113
descriptor.h
113
descriptor.h
@ -34,37 +34,38 @@ typedef struct _FLASH_DESCRIPTOR_HEADER {
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// Descriptor map
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// Base fields are storing bits [11:4] of actual base addresses, all other bits are 0
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typedef struct _FLASH_DESCRIPTOR_MAP {
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UINT8 ComponentBase; // 0x03 on most machines
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UINT8 NumberOfFlashChips; // Zero-based number of flash chips installed on board
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UINT8 RegionBase; // 0x04 on most machines
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UINT8 NumberOfRegions; // Zero-based number of flash regions (descriptor is always included)
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UINT8 MasterBase; // 0x06 on most machines
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UINT8 NumberOfMasters; // Zero-based number of flash masters
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UINT8 PchStrapsBase; // 0x10 on most machines
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UINT8 NumberOfPchStraps; // One-based number of UINT32s to read as PCH Straps, min=0, max=255 (1 Kb)
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UINT8 ProcStrapsBase; // 0x20 on most machines
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UINT8 NumberOfProcStraps; // Number of PROC straps to be read, can be 0 or 1
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UINT8 IccTableBase; // 0x21 on most machines
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UINT8 NumberOfIccTableEntries; // 0x00 on most machines
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UINT8 DmiTableBase; // 0x25 on most machines
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UINT8 NumberOfDmiTableEntries; // 0x00 on most machines
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UINT16 ReservedZero; // Still unknown, zeros in all descriptors I have seen
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// FLMAP0
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UINT32 ComponentBase : 8;
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UINT32 NumberOfFlashChips : 2; // Zero-based number of flash chips installed on board
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UINT32 : 6;
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UINT32 RegionBase : 8;
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UINT32 : 8;
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// FLMAP 1
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UINT32 MasterBase : 8;
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UINT32 NumberOfMasters : 2;
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UINT32 : 6;
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UINT32 PchStrapsBase : 8;
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UINT32 NumberOfPchStraps : 8; // One-based number of UINT32s to read as PCH straps, min=0, max=255 (1 Kb)
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// FLMAP 2
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UINT32 ProcStrapsBase : 8;
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UINT32 NumberOfProcStraps : 8; // One-based number of UINT32s to read as processor straps, min=0, max=255 (1 Kb)
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UINT32: 16;
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} FLASH_DESCRIPTOR_MAP;
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// Component section
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// Flash parameters DWORD structure
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typedef struct _FLASH_PARAMETERS {
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UINT8 FirstChipDensity : 3;
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UINT8 SecondChipDensity : 3;
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UINT8 ReservedZero0 : 2; // Still unknown, zeros in all descriptors I have seen
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UINT8 ReservedZero1 : 8; // Still unknown, zeros in all descriptors I have seen
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UINT8 ReservedZero2 : 4; // Still unknown, zeros in all descriptors I have seen
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UINT8 FirstChipDensity : 4;
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UINT8 SecondChipDensity : 4;
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UINT8 : 8;
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UINT8 : 1;
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UINT8 ReadClockFreqency : 3; // Hardcoded value of 20 Mhz (000b) in v1 descriptors and 17 Mhz (110b) in v2 ones
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UINT8 FastReadEnabled : 1;
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UINT8 FastReadFreqency : 3;
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UINT8 FlashReadStatusFrequency : 3;
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UINT8 FlashWriteFrequency : 3;
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UINT8 DualOutputFastReadSupported : 1;
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UINT8 ReservedZero3 : 1; // Still unknown, zero in all descriptors I have seen
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UINT8 : 1;
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} FLASH_PARAMETERS;
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// Flash densities
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@ -74,11 +75,16 @@ typedef struct _FLASH_PARAMETERS {
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#define FLASH_DENSITY_4MB 0x03
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#define FLASH_DENSITY_8MB 0x04
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#define FLASH_DENSITY_16MB 0x05
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#define FLASH_DENSITY_32MB 0x06
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#define FLASH_DENSITY_64MB 0x07
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#define FLASH_DENSITY_UNUSED 0x0F
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// Flash frequencies
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#define FLASH_FREQUENCY_20MHZ 0x00
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#define FLASH_FREQUENCY_33MHZ 0x01
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#define FLASH_FREQUENCY_50MHZ 0x04
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#define FLASH_FREQUENCY_48MHZ 0x02
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#define FLASH_FREQUENCY_50MHZ_30MHZ 0x04
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#define FLASH_FREQUENCY_17MHZ 0x06
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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@ -87,24 +93,45 @@ typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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UINT8 InvalidInstruction1; //
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UINT8 InvalidInstruction2; //
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UINT8 InvalidInstruction3; //
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UINT16 PartitionBoundary; // Upper 16 bit of partition boundary address. Default is 0x0000, which makes the boundary to be 0x00001000
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UINT16 ReservedZero; // Still unknown, zero in all descriptors I have seen
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} FLASH_DESCRIPTOR_COMPONENT_SECTION;
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION_V2 {
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FLASH_PARAMETERS FlashParameters;
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UINT8 InvalidInstruction0; // Instructions for SPI chip, that must not be executed, like FLASH ERASE
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UINT8 InvalidInstruction1; //
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UINT8 InvalidInstruction2; //
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UINT8 InvalidInstruction3; //
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UINT8 InvalidInstruction4; //
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UINT8 InvalidInstruction5; //
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UINT8 InvalidInstruction6; //
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UINT8 InvalidInstruction7; //
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} FLASH_DESCRIPTOR_COMPONENT_SECTION_V2;
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// Region section
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// All base and limit register are storing upper part of actual UINT32 base and limit
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// If limit is zero - region is not present
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typedef struct _FLASH_DESCRIPTOR_REGION_SECTION {
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UINT16 ReservedZero; // Still unknown, zero in all descriptors I have seen
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UINT16 :16;
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UINT16 FlashBlockEraseSize; // Size of block erased by single BLOCK ERASE command
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UINT16 BiosBase;
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UINT16 BiosLimit;
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UINT16 MeBase;
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UINT16 MeLimit;
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UINT16 GbeBase;
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UINT16 GbeLimit;
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UINT16 PdrBase;
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UINT16 PdrLimit;
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UINT16 Region0Base; // BIOS
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UINT16 Region0Limit; //
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UINT16 Region1Base; // ME
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UINT16 Region1Limit; //
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UINT16 Region2Base; // GbE
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UINT16 Region2Limit; //
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UINT16 Region3Base; // PDR
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UINT16 Region3Limit; //
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UINT16 Region4Base; // Reserved region
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UINT16 Region4Limit; //
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UINT16 Region5Base; // Reserved region
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UINT16 Region5Limit; //
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UINT16 Region6Base; // Reserved region
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UINT16 Region6Limit; //
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UINT16 Region7Base; // Reserved region
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UINT16 Region7Limit; //
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UINT16 Region8Base; // EC
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UINT16 Region8Limit; //
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} FLASH_DESCRIPTOR_REGION_SECTION;
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// Flash block erase sizes
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@ -125,14 +152,30 @@ typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION {
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UINT8 GbeWrite;
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} FLASH_DESCRIPTOR_MASTER_SECTION;
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// Master section v2 (Skylake+)
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION_V2 {
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UINT32 : 8;
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UINT32 BiosRead : 12;
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UINT32 BiosWrite : 12;
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UINT32 : 8;
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UINT32 MeRead : 12;
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UINT32 MeWrite : 12;
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UINT32 : 8;
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UINT32 GbeRead : 12;
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UINT32 GbeWrite : 12;
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UINT32 :32;
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UINT32 : 8;
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UINT32 EcRead : 12;
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UINT32 EcWrite : 12;
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} FLASH_DESCRIPTOR_MASTER_SECTION_V2;
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// Region access bits in master section
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#define FLASH_DESCRIPTOR_REGION_ACCESS_DESC 0x01
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#define FLASH_DESCRIPTOR_REGION_ACCESS_BIOS 0x02
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#define FLASH_DESCRIPTOR_REGION_ACCESS_ME 0x04
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#define FLASH_DESCRIPTOR_REGION_ACCESS_GBE 0x08
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#define FLASH_DESCRIPTOR_REGION_ACCESS_PDR 0x10
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//!TODO: Describe PCH and PROC straps sections, as well as ICC and DMI tables
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#define FLASH_DESCRIPTOR_REGION_ACCESS_EC 0x20
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// Base address of descriptor upper map
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#define FLASH_DESCRIPTOR_UPPER_MAP_BASE 0x0EFC
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4
ffs.h
4
ffs.h
@ -53,10 +53,6 @@ const QByteArray EFI_CAPSULE_GUID
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const QByteArray INTEL_CAPSULE_GUID
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("\xB9\x82\x91\x53\xB5\xAB\x91\x43\xB6\x9A\xE3\xA9\x43\xF7\x2F\xCC", 16);
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// Lenovo capsule GUID
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const QByteArray LENOVO_CAPSULE_GUID
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("\x8B\xA6\x3C\x4A\x23\x77\xFB\x48\x80\x3D\x57\x8C\xC1\xFE\xC4\x4D", 16);
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// Toshiba EFI Capsule header
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typedef struct _TOSHIBA_CAPSULE_HEADER {
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EFI_GUID CapsuleGuid;
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244
ffsengine.cpp
244
ffsengine.cpp
@ -155,8 +155,7 @@ UINT8 FfsEngine::parseImageFile(const QByteArray & buffer)
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UINT32 capsuleHeaderSize = 0;
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QModelIndex index;
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if (buffer.startsWith(EFI_CAPSULE_GUID)
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|| buffer.startsWith(INTEL_CAPSULE_GUID)
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|| buffer.startsWith(LENOVO_CAPSULE_GUID)) {
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|| buffer.startsWith(INTEL_CAPSULE_GUID)) {
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// Get info
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const EFI_CAPSULE_HEADER* capsuleHeader = (const EFI_CAPSULE_HEADER*)buffer.constData();
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capsuleHeaderSize = capsuleHeader->HeaderSize;
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@ -266,45 +265,36 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
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const FLASH_DESCRIPTOR_MAP* descriptorMap = (const FLASH_DESCRIPTOR_MAP*)(descriptor + sizeof(FLASH_DESCRIPTOR_HEADER));
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const FLASH_DESCRIPTOR_UPPER_MAP* upperMap = (const FLASH_DESCRIPTOR_UPPER_MAP*)(descriptor + FLASH_DESCRIPTOR_UPPER_MAP_BASE);
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const FLASH_DESCRIPTOR_REGION_SECTION* regionSection = (const FLASH_DESCRIPTOR_REGION_SECTION*)calculateAddress8(descriptor, descriptorMap->RegionBase);
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const FLASH_DESCRIPTOR_MASTER_SECTION* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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const FLASH_DESCRIPTOR_COMPONENT_SECTION* componentSection = (const FLASH_DESCRIPTOR_COMPONENT_SECTION*)calculateAddress8(descriptor, descriptorMap->ComponentBase);
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// GbE region
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QByteArray gbe;
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UINT32 gbeBegin = 0;
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UINT32 gbeEnd = 0;
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if (regionSection->GbeLimit) {
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gbeBegin = calculateRegionOffset(regionSection->GbeBase);
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gbeEnd = calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
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gbe = intelImage.mid(gbeBegin, gbeEnd);
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gbeEnd += gbeBegin;
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// Check descriptor version by getting hardcoded value of FlashParameters.ReadClockFrequency
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UINT8 descriptorVersion = 0;
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if (componentSection->FlashParameters.ReadClockFreqency == FLASH_FREQUENCY_20MHZ) // Old descriptor
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descriptorVersion = 1;
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else if (componentSection->FlashParameters.ReadClockFreqency == FLASH_FREQUENCY_17MHZ) // Skylake+ descriptor
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descriptorVersion = 2;
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else {
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msg(tr("parseIntelImage: unknown descriptor version with ReadClockFreqency %1h").hexarg(componentSection->FlashParameters.ReadClockFreqency));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// ME region
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QByteArray me;
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UINT32 meBegin = 0;
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UINT32 meEnd = 0;
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if (regionSection->MeLimit) {
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meBegin = calculateRegionOffset(regionSection->MeBase);
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meEnd = calculateRegionSize(regionSection->MeBase, regionSection->MeLimit);
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if (regionSection->Region1Limit) {
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meBegin = calculateRegionOffset(regionSection->Region1Base);
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meEnd = calculateRegionSize(regionSection->Region1Base, regionSection->Region1Limit);
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me = intelImage.mid(meBegin, meEnd);
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meEnd += meBegin;
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}
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// PDR region
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QByteArray pdr;
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UINT32 pdrBegin = 0;
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UINT32 pdrEnd = 0;
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if (regionSection->PdrLimit) {
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pdrBegin = calculateRegionOffset(regionSection->PdrBase);
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pdrEnd = calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
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pdr = intelImage.mid(pdrBegin, pdrEnd);
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pdrEnd += pdrBegin;
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}
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// BIOS region
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QByteArray bios;
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UINT32 biosBegin = 0;
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UINT32 biosEnd = 0;
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if (regionSection->BiosLimit) {
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biosBegin = calculateRegionOffset(regionSection->BiosBase);
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biosEnd = calculateRegionSize(regionSection->BiosBase, regionSection->BiosLimit);
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if (regionSection->Region0Limit) {
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biosBegin = calculateRegionOffset(regionSection->Region0Base);
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biosEnd = calculateRegionSize(regionSection->Region0Base, regionSection->Region0Limit);
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// Check for Gigabyte specific descriptor map
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if (biosEnd - biosBegin == (UINT32)intelImage.size()) {
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@ -322,8 +312,41 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region not found in descriptor"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// GbE region
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QByteArray gbe;
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UINT32 gbeBegin = 0;
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UINT32 gbeEnd = 0;
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if (regionSection->Region2Limit) {
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gbeBegin = calculateRegionOffset(regionSection->Region2Base);
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gbeEnd = calculateRegionSize(regionSection->Region2Base, regionSection->Region2Limit);
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gbe = intelImage.mid(gbeBegin, gbeEnd);
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gbeEnd += gbeBegin;
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}
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// PDR region
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QByteArray pdr;
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UINT32 pdrBegin = 0;
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UINT32 pdrEnd = 0;
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if (regionSection->Region3Limit) {
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pdrBegin = calculateRegionOffset(regionSection->Region3Base);
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pdrEnd = calculateRegionSize(regionSection->Region3Base, regionSection->Region3Limit);
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pdr = intelImage.mid(pdrBegin, pdrEnd);
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pdrEnd += pdrBegin;
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}
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// EC region
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QByteArray ec;
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UINT32 ecBegin = 0;
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UINT32 ecEnd = 0;
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if (descriptorVersion == 2) {
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if (regionSection->Region8Limit) {
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pdrBegin = calculateRegionOffset(regionSection->Region8Base);
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pdrEnd = calculateRegionSize(regionSection->Region8Base, regionSection->Region8Limit);
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pdr = intelImage.mid(ecBegin, ecEnd);
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ecEnd += ecBegin;
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}
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}
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// Check for intersections between regions
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// Descriptor
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if (hasIntersection(descriptorBegin, descriptorEnd, gbeBegin, gbeEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with GbE region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -340,6 +363,11 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(descriptorBegin, descriptorEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// GbE
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if (hasIntersection(gbeBegin, gbeEnd, meBegin, meEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with ME region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -352,6 +380,11 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(gbeBegin, gbeEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// ME
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if (hasIntersection(meBegin, meEnd, biosBegin, biosEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with BIOS region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -360,23 +393,35 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(meBegin, meEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// BIOS
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if (hasIntersection(biosBegin, biosEnd, pdrBegin, pdrEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(biosBegin, biosEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// PDR
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if (descriptorVersion == 2 && hasIntersection(pdrBegin, pdrEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, PDR region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// Region map is consistent
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// Intel image
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QString name = tr("Intel image");
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QString info = tr("Full size: %1h (%2)\nFlash chips: %3\nRegions: %4\nMasters: %5\nPCH straps: %6\nPROC straps: %7\nICC table entries: %8")
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QString info = tr("Full size: %1h (%2)\nFlash chips: %3\nMasters: %4\nPCH straps: %5\nCPU straps: %6\n")
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.hexarg(intelImage.size()).arg(intelImage.size())
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.arg(descriptorMap->NumberOfFlashChips + 1) //
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.arg(descriptorMap->NumberOfRegions + 1) // Zero-based numbers in storage
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.arg(descriptorMap->NumberOfMasters + 1) //
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.arg(descriptorMap->NumberOfFlashChips + 1)
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.arg(descriptorMap->NumberOfMasters + 1)
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.arg(descriptorMap->NumberOfPchStraps)
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.arg(descriptorMap->NumberOfProcStraps)
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.arg(descriptorMap->NumberOfIccTableEntries);
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.arg(descriptorMap->NumberOfProcStraps);
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// Add Intel image tree item
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index = model->addItem(Types::Image, Subtypes::IntelImage, COMPRESSION_ALGORITHM_NONE, name, "", info, QByteArray(), intelImage, parent);
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@ -389,24 +434,30 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
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// Check regions presence once again
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QVector<UINT32> offsets;
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if (regionSection->GbeLimit) {
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if (regionSection->Region2Limit) {
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offsets.append(gbeBegin);
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info += tr("\nGbE region offset: %1h").hexarg(gbeBegin);
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}
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if (regionSection->MeLimit) {
|
||||
if (regionSection->Region1Limit) {
|
||||
offsets.append(meBegin);
|
||||
info += tr("\nME region offset: %1h").hexarg(meBegin);
|
||||
}
|
||||
if (regionSection->BiosLimit) {
|
||||
if (regionSection->Region0Limit) {
|
||||
offsets.append(biosBegin);
|
||||
info += tr("\nBIOS region offset: %1h").hexarg(biosBegin);
|
||||
}
|
||||
if (regionSection->PdrLimit) {
|
||||
if (regionSection->Region3Limit) {
|
||||
offsets.append(pdrBegin);
|
||||
info += tr("\nPDR region offset: %1h").hexarg(pdrBegin);
|
||||
}
|
||||
if (descriptorVersion == 2 && regionSection->Region8Limit) {
|
||||
offsets.append(ecBegin);
|
||||
info += tr("\nEC region offset: %1h").hexarg(ecBegin);
|
||||
}
|
||||
|
||||
// Region access settings
|
||||
if (descriptorVersion == 1) {
|
||||
const FLASH_DESCRIPTOR_MASTER_SECTION* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION*)calculateAddress8(descriptor, descriptorMap->MasterBase);
|
||||
info += tr("\nRegion access settings:");
|
||||
info += tr("\nBIOS:%1%2h ME:%3%4h GbE:%5%6h")
|
||||
.hexarg2(masterSection->BiosRead, 2)
|
||||
@ -432,6 +483,40 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
||||
info += tr("\nPDR %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
|
||||
}
|
||||
else if (descriptorVersion == 2) {
|
||||
const FLASH_DESCRIPTOR_MASTER_SECTION_V2* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION_V2*)calculateAddress8(descriptor, descriptorMap->MasterBase);
|
||||
info += tr("\nRegion access settings:");
|
||||
info += tr("\nBIOS: %1h %2h ME: %3h %4h\nGbE: %5h %6h EC: %7h %8h")
|
||||
.hexarg2(masterSection->BiosRead, 3)
|
||||
.hexarg2(masterSection->BiosWrite, 3)
|
||||
.hexarg2(masterSection->MeRead, 3)
|
||||
.hexarg2(masterSection->MeWrite, 3)
|
||||
.hexarg2(masterSection->GbeRead, 3)
|
||||
.hexarg2(masterSection->GbeWrite, 3)
|
||||
.hexarg2(masterSection->EcRead, 3)
|
||||
.hexarg2(masterSection->EcWrite, 3);
|
||||
|
||||
// BIOS access table
|
||||
info += tr("\nBIOS access table:");
|
||||
info += tr("\n Read Write");
|
||||
info += tr("\nDesc %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ");
|
||||
info += tr("\nBIOS Yes Yes");
|
||||
info += tr("\nME %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ");
|
||||
info += tr("\nGbE %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ");
|
||||
info += tr("\nPDR %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
|
||||
info += tr("\nEC %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_EC ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_EC ? "Yes " : "No ");
|
||||
}
|
||||
|
||||
// VSCC table
|
||||
const VSCC_TABLE_ENTRY* vsccTableEntry = (const VSCC_TABLE_ENTRY*)(descriptor + ((UINT16)upperMap->VsccTableBase << 4));
|
||||
@ -474,6 +559,11 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
||||
QModelIndex pdrIndex;
|
||||
result = parsePdrRegion(pdr, pdrIndex, index);
|
||||
}
|
||||
// Parse EC region
|
||||
else if (descriptorVersion == 2 && offsets.at(i) == ecBegin) {
|
||||
QModelIndex ecIndex;
|
||||
result = parseEcRegion(ec, ecIndex, index);
|
||||
}
|
||||
if (result)
|
||||
return result;
|
||||
}
|
||||
@ -489,6 +579,8 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
||||
IntelDataEnd = biosEnd;
|
||||
else if (LastRegionOffset == pdrBegin)
|
||||
IntelDataEnd = pdrEnd;
|
||||
else if (descriptorVersion == 2 && LastRegionOffset == ecBegin)
|
||||
IntelDataEnd = ecEnd;
|
||||
|
||||
if (IntelDataEnd > (UINT32)intelImage.size()) { // Image file is truncated
|
||||
msg(tr("parseIntelImage: image size %1 (%2) is smaller than the end of last region %3 (%4), may be damaged")
|
||||
@ -615,6 +707,23 @@ UINT8 FfsEngine::parsePdrRegion(const QByteArray & pdr, QModelIndex & index, con
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
UINT8 FfsEngine::parseEcRegion(const QByteArray & ec, QModelIndex & index, const QModelIndex & parent, const UINT8 mode)
|
||||
{
|
||||
// Check sanity
|
||||
if (ec.isEmpty())
|
||||
return ERR_EMPTY_REGION;
|
||||
|
||||
// Get info
|
||||
QString name = tr("EC region");
|
||||
QString info = tr("Full size: %1h (%2)").
|
||||
hexarg(ec.size()).arg(ec.size());
|
||||
|
||||
// Add tree item
|
||||
index = model->addItem(Types::Region, Subtypes::EcRegion, COMPRESSION_ALGORITHM_NONE, name, "", info, QByteArray(), ec, parent, mode);
|
||||
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
UINT8 FfsEngine::parseBiosRegion(const QByteArray & bios, QModelIndex & index, const QModelIndex & parent, const UINT8 mode)
|
||||
{
|
||||
if (bios.isEmpty())
|
||||
@ -928,10 +1037,10 @@ UINT8 FfsEngine::parseVolume(const QByteArray & volume, QModelIndex & index, co
|
||||
// All the rest is either free space or non-UEFI data
|
||||
QByteArray rest = volume.right(volumeSize - fileOffset);
|
||||
if (rest.count(empty) == rest.size()) { // It's a free space
|
||||
model->addItem(Types::FreeSpace, 0, COMPRESSION_ALGORITHM_NONE, tr("Volume free space"), "", tr("Full size: %1h (%2)").hexarg(rest.size()).arg(rest.size()), QByteArray(), rest, index, mode);
|
||||
model->addItem(Types::FreeSpace, 0, COMPRESSION_ALGORITHM_NONE, tr("Volume free space"), "", tr("Full size: %1h (%2)").hexarg(rest.size()).arg(rest.size()), QByteArray(), rest, index);
|
||||
}
|
||||
else { //It's non-UEFI data
|
||||
QModelIndex dataIndex = model->addItem(Types::Padding, Subtypes::DataPadding, COMPRESSION_ALGORITHM_NONE, tr("Non-UEFI data"), "", tr("Full size: %1h (%2)").hexarg(rest.size()).arg(rest.size()), QByteArray(), rest, index, mode);
|
||||
QModelIndex dataIndex = model->addItem(Types::Padding, Subtypes::DataPadding, COMPRESSION_ALGORITHM_NONE, tr("Non-UEFI data"), "", tr("Full size: %1h (%2)").hexarg(rest.size()).arg(rest.size()), QByteArray(), rest, index);
|
||||
msg(tr("parseVolume: non-UEFI data found in volume's free space"), dataIndex);
|
||||
}
|
||||
// Exit from loop
|
||||
@ -973,16 +1082,16 @@ UINT8 FfsEngine::parseVolume(const QByteArray & volume, QModelIndex & index, co
|
||||
// Add all bytes before as free space...
|
||||
if (i > 0) {
|
||||
QByteArray free = freeSpace.left(i);
|
||||
model->addItem(Types::FreeSpace, 0, COMPRESSION_ALGORITHM_NONE, tr("Volume free space"), "", tr("Full size: %1h (%2)").hexarg(free.size()).arg(free.size()), QByteArray(), free, index, mode);
|
||||
model->addItem(Types::FreeSpace, 0, COMPRESSION_ALGORITHM_NONE, tr("Volume free space"), "", tr("Full size: %1h (%2)").hexarg(free.size()).arg(free.size()), QByteArray(), free, index);
|
||||
}
|
||||
// ... and all bytes after as a padding
|
||||
QByteArray padding = freeSpace.mid(i);
|
||||
QModelIndex dataIndex = model->addItem(Types::Padding, Subtypes::DataPadding, COMPRESSION_ALGORITHM_NONE, tr("Non-UEFI data"), "", tr("Full size: %1h (%2)").hexarg(padding.size()).arg(padding.size()), QByteArray(), padding, index, mode);
|
||||
QModelIndex dataIndex = model->addItem(Types::Padding, Subtypes::DataPadding, COMPRESSION_ALGORITHM_NONE, tr("Non-UEFI data"), "", tr("Full size: %1h (%2)").hexarg(padding.size()).arg(padding.size()), QByteArray(), padding, index);
|
||||
msg(tr("parseVolume: non-UEFI data found in volume's free space"), dataIndex);
|
||||
}
|
||||
else {
|
||||
// Add free space element
|
||||
model->addItem(Types::FreeSpace, 0, COMPRESSION_ALGORITHM_NONE, tr("Volume free space"), "", tr("Full size: %1h (%2)").hexarg(freeSpace.size()).arg(freeSpace.size()), QByteArray(), freeSpace, index, mode);
|
||||
model->addItem(Types::FreeSpace, 0, COMPRESSION_ALGORITHM_NONE, tr("Volume free space"), "", tr("Full size: %1h (%2)").hexarg(freeSpace.size()).arg(freeSpace.size()), QByteArray(), freeSpace, index);
|
||||
}
|
||||
break; // Exit from loop
|
||||
}
|
||||
@ -1989,7 +2098,7 @@ UINT8 FfsEngine::create(const QModelIndex & index, const UINT8 type, const QByte
|
||||
if (header.isEmpty()) // Whole volume
|
||||
volume.append(body);
|
||||
else { // Body only
|
||||
volume.append(model->header(index)).append(body);
|
||||
volume.append(header).append(body);
|
||||
INT32 sizeDiff = model->body(index).size() - body.size();
|
||||
if (sizeDiff > 0) {
|
||||
const EFI_FIRMWARE_VOLUME_HEADER* volumeHeader = (const EFI_FIRMWARE_VOLUME_HEADER*)model->header(index).constData();
|
||||
@ -2704,17 +2813,37 @@ UINT8 FfsEngine::reconstructIntelImage(const QModelIndex& index, QByteArray& rec
|
||||
const FLASH_DESCRIPTOR_MAP* descriptorMap = (const FLASH_DESCRIPTOR_MAP*)(descriptor.constData() + sizeof(FLASH_DESCRIPTOR_HEADER));
|
||||
const FLASH_DESCRIPTOR_REGION_SECTION* regionSection = (const FLASH_DESCRIPTOR_REGION_SECTION*)calculateAddress8((const UINT8*)descriptor.constData(), descriptorMap->RegionBase);
|
||||
QByteArray gbe;
|
||||
UINT32 gbeBegin = calculateRegionOffset(regionSection->GbeBase);
|
||||
UINT32 gbeEnd = gbeBegin + calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
|
||||
UINT32 gbeBegin = calculateRegionOffset(regionSection->Region2Base);
|
||||
UINT32 gbeEnd = gbeBegin + calculateRegionSize(regionSection->Region2Base, regionSection->Region2Limit);
|
||||
QByteArray me;
|
||||
UINT32 meBegin = calculateRegionOffset(regionSection->MeBase);
|
||||
UINT32 meEnd = meBegin + calculateRegionSize(regionSection->MeBase, regionSection->MeLimit);
|
||||
UINT32 meBegin = calculateRegionOffset(regionSection->Region1Base);
|
||||
UINT32 meEnd = meBegin + calculateRegionSize(regionSection->Region1Base, regionSection->Region1Limit);
|
||||
QByteArray bios;
|
||||
UINT32 biosBegin = calculateRegionOffset(regionSection->BiosBase);
|
||||
UINT32 biosEnd = biosBegin + calculateRegionSize(regionSection->BiosBase, regionSection->BiosLimit);
|
||||
UINT32 biosBegin = calculateRegionOffset(regionSection->Region0Base);
|
||||
UINT32 biosEnd = biosBegin + calculateRegionSize(regionSection->Region0Base, regionSection->Region0Limit);
|
||||
QByteArray pdr;
|
||||
UINT32 pdrBegin = calculateRegionOffset(regionSection->PdrBase);
|
||||
UINT32 pdrEnd = pdrBegin + calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
|
||||
UINT32 pdrBegin = calculateRegionOffset(regionSection->Region3Base);
|
||||
UINT32 pdrEnd = pdrBegin + calculateRegionSize(regionSection->Region3Base, regionSection->Region3Limit);
|
||||
QByteArray ec;
|
||||
UINT32 ecBegin = 0;
|
||||
UINT32 ecEnd = 0;
|
||||
|
||||
const FLASH_DESCRIPTOR_COMPONENT_SECTION* componentSection = (const FLASH_DESCRIPTOR_COMPONENT_SECTION*)calculateAddress8((const UINT8*)descriptor.constData(), descriptorMap->ComponentBase);
|
||||
// Check descriptor version by getting hardcoded value of FlashParameters.ReadClockFrequency
|
||||
UINT8 descriptorVersion = 0;
|
||||
if (componentSection->FlashParameters.ReadClockFreqency == FLASH_FREQUENCY_20MHZ) { // Old descriptor
|
||||
descriptorVersion = 1;
|
||||
}
|
||||
else if (componentSection->FlashParameters.ReadClockFreqency == FLASH_FREQUENCY_17MHZ) { // Skylake+ descriptor
|
||||
descriptorVersion = 2;
|
||||
ecBegin = calculateRegionOffset(regionSection->Region8Base);
|
||||
ecEnd = ecBegin + calculateRegionSize(regionSection->Region8Base, regionSection->Region8Limit);
|
||||
}
|
||||
else {
|
||||
msg(tr("reconstructIntelImage: unknown descriptor version with ReadClockFreqency %1h").hexarg(componentSection->FlashParameters.ReadClockFreqency));
|
||||
return ERR_INVALID_FLASH_DESCRIPTOR;
|
||||
}
|
||||
|
||||
|
||||
UINT32 offset = descriptor.size();
|
||||
// Reconstruct other regions
|
||||
@ -2764,6 +2893,17 @@ UINT8 FfsEngine::reconstructIntelImage(const QModelIndex& index, QByteArray& rec
|
||||
reconstructed.append(pdr);
|
||||
offset = pdrEnd;
|
||||
break;
|
||||
case Subtypes::EcRegion:
|
||||
if (descriptorVersion == 1) {
|
||||
msg(tr("reconstructIntelImage: incompatible region type found"), index);
|
||||
return ERR_INVALID_REGION;
|
||||
}
|
||||
ec = region;
|
||||
if (ecBegin > offset)
|
||||
reconstructed.append(QByteArray(ecBegin - offset, empty));
|
||||
reconstructed.append(ec);
|
||||
offset = ecEnd;
|
||||
break;
|
||||
default:
|
||||
msg(tr("reconstructIntelImage: unknown region type found"), index);
|
||||
return ERR_INVALID_REGION;
|
||||
|
||||
@ -67,6 +67,7 @@ public:
|
||||
UINT8 parseMeRegion(const QByteArray & me, QModelIndex & index, const QModelIndex & parent, const UINT8 mode = CREATE_MODE_APPEND);
|
||||
UINT8 parseBiosRegion(const QByteArray & bios, QModelIndex & index, const QModelIndex & parent, const UINT8 mode = CREATE_MODE_APPEND);
|
||||
UINT8 parsePdrRegion(const QByteArray & pdr, QModelIndex & index, const QModelIndex & parent, const UINT8 mode = CREATE_MODE_APPEND);
|
||||
UINT8 parseEcRegion(const QByteArray & ec, QModelIndex & index, const QModelIndex & parent, const UINT8 mode = CREATE_MODE_APPEND);
|
||||
UINT8 parseBios(const QByteArray & bios, const QModelIndex & parent = QModelIndex());
|
||||
UINT8 parseVolume(const QByteArray & volume, QModelIndex & index, const QModelIndex & parent = QModelIndex(), const UINT8 mode = CREATE_MODE_APPEND);
|
||||
UINT8 parseFile(const QByteArray & file, QModelIndex & index, const UINT8 erasePolarity = ERASE_POLARITY_UNKNOWN, const QModelIndex & parent = QModelIndex(), const UINT8 mode = CREATE_MODE_APPEND);
|
||||
|
||||
@ -29,6 +29,8 @@ QString regionTypeToQString(const UINT8 type)
|
||||
return QObject::tr("BIOS");
|
||||
case Subtypes::PdrRegion:
|
||||
return QObject::tr("PDR");
|
||||
case Subtypes::EcRegion:
|
||||
return QObject::tr("EC");
|
||||
default:
|
||||
return QObject::tr("Unknown");
|
||||
};
|
||||
|
||||
3
types.h
3
types.h
@ -69,7 +69,8 @@ namespace Subtypes {
|
||||
GbeRegion,
|
||||
MeRegion,
|
||||
BiosRegion,
|
||||
PdrRegion
|
||||
PdrRegion,
|
||||
EcRegion
|
||||
};
|
||||
|
||||
enum PaddingSubtypes {
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
UEFITool::UEFITool(QWidget *parent) :
|
||||
QMainWindow(parent),
|
||||
ui(new Ui::UEFITool),
|
||||
version(tr("0.20.8"))
|
||||
version(tr("0.21.0"))
|
||||
{
|
||||
clipboard = QApplication::clipboard();
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user