mirror of
https://github.com/LongSoft/UEFITool.git
synced 2024-11-22 07:58:22 +08:00
Port of latest descriptor handling changes from master
- added Skylake+ descriptor format support
This commit is contained in:
Nikolaj Schlej
parent
d36951da88
commit
b8317ac4f2
@ -17,7 +17,7 @@
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UEFITool::UEFITool(QWidget *parent) :
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QMainWindow(parent),
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ui(new Ui::UEFITool),
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version(tr("0.30.0_alpha8"))
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version(tr("0.30.0_alpha9"))
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{
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clipboard = QApplication::clipboard();
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@ -34,37 +34,39 @@ typedef struct _FLASH_DESCRIPTOR_HEADER {
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// Descriptor map
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// Base fields are storing bits [11:4] of actual base addresses, all other bits are 0
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typedef struct _FLASH_DESCRIPTOR_MAP {
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UINT8 ComponentBase; // 0x03 on most machines
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UINT8 NumberOfFlashChips; // Zero-based number of flash chips installed on board
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UINT8 RegionBase; // 0x04 on most machines
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UINT8 NumberOfRegions; // Zero-based number of flash regions (descriptor is always included)
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UINT8 MasterBase; // 0x06 on most machines
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UINT8 NumberOfMasters; // Zero-based number of flash masters
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UINT8 PchStrapsBase; // 0x10 on most machines
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UINT8 NumberOfPchStraps; // One-based number of UINT32s to read as PCH Straps, min=0, max=255 (1 Kb)
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UINT8 ProcStrapsBase; // 0x20 on most machines
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UINT8 NumberOfProcStraps; // Number of PROC straps to be read, can be 0 or 1
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UINT8 IccTableBase; // 0x21 on most machines
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UINT8 NumberOfIccTableEntries; // 0x00 on most machines
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UINT8 DmiTableBase; // 0x25 on most machines
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UINT8 NumberOfDmiTableEntries; // 0x00 on most machines
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UINT16 ReservedZero; // Still unknown, zeros in all descriptors I have seen
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// FLMAP0
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UINT32 ComponentBase : 8;
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UINT32 NumberOfFlashChips : 2; // Zero-based number of flash chips installed on board
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UINT32 : 6;
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UINT32 RegionBase : 8;
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UINT32 NumberOfRegions : 3; // Reserved in v2 descriptor
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UINT32 : 5;
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// FLMAP 1
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UINT32 MasterBase : 8;
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UINT32 NumberOfMasters : 2; // Zero-based number of flash masters
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UINT32 : 6;
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UINT32 PchStrapsBase : 8;
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UINT32 NumberOfPchStraps : 8; // One-based number of UINT32s to read as PCH straps, min=0, max=255 (1 Kb)
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// FLMAP 2
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UINT32 ProcStrapsBase : 8;
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UINT32 NumberOfProcStraps : 8; // One-based number of UINT32s to read as processor straps, min=0, max=255 (1 Kb)
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UINT32 : 16;
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} FLASH_DESCRIPTOR_MAP;
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// Component section
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// Flash parameters DWORD structure
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typedef struct _FLASH_PARAMETERS {
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UINT8 FirstChipDensity : 3;
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UINT8 SecondChipDensity : 3;
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UINT8 ReservedZero0 : 2; // Still unknown, zeros in all descriptors I have seen
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UINT8 ReservedZero1 : 8; // Still unknown, zeros in all descriptors I have seen
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UINT8 ReservedZero2 : 4; // Still unknown, zeros in all descriptors I have seen
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UINT8 FirstChipDensity : 4;
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UINT8 SecondChipDensity : 4;
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UINT8 : 8;
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UINT8 : 1;
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UINT8 ReadClockFrequency : 3; // Hardcoded value of 20 Mhz (000b) in v1 descriptors and 17 Mhz (110b) in v2 ones
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UINT8 FastReadEnabled : 1;
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UINT8 FastReadFreqency : 3;
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UINT8 FlashReadStatusFrequency : 3;
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UINT8 FastReadFrequency : 3;
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UINT8 FlashWriteFrequency : 3;
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UINT8 FlashReadStatusFrequency : 3;
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UINT8 DualOutputFastReadSupported : 1;
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UINT8 ReservedZero3 : 1; // Still unknown, zero in all descriptors I have seen
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UINT8 : 1;
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} FLASH_PARAMETERS;
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// Flash densities
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@ -74,11 +76,16 @@ typedef struct _FLASH_PARAMETERS {
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#define FLASH_DENSITY_4MB 0x03
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#define FLASH_DENSITY_8MB 0x04
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#define FLASH_DENSITY_16MB 0x05
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#define FLASH_DENSITY_32MB 0x06
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#define FLASH_DENSITY_64MB 0x07
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#define FLASH_DENSITY_UNUSED 0x0F
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// Flash frequencies
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#define FLASH_FREQUENCY_20MHZ 0x00
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#define FLASH_FREQUENCY_33MHZ 0x01
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#define FLASH_FREQUENCY_50MHZ 0x04
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#define FLASH_FREQUENCY_48MHZ 0x02
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#define FLASH_FREQUENCY_50MHZ_30MHZ 0x04
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#define FLASH_FREQUENCY_17MHZ 0x06
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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@ -95,23 +102,28 @@ typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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// All base and limit register are storing upper part of actual UINT32 base and limit
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// If limit is zero - region is not present
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typedef struct _FLASH_DESCRIPTOR_REGION_SECTION {
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UINT16 ReservedZero; // Still unknown, zero in all descriptors I have seen
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UINT16 FlashBlockEraseSize; // Size of block erased by single BLOCK ERASE command
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UINT16 BiosBase;
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UINT16 BiosLimit;
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UINT16 MeBase;
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UINT16 MeLimit;
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UINT16 GbeBase;
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UINT16 GbeLimit;
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UINT16 PdrBase;
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UINT16 PdrLimit;
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UINT16 DescriptorBase; // Descriptor
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UINT16 DescriptorLimit; //
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UINT16 BiosBase; // BIOS
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UINT16 BiosLimit; //
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UINT16 MeBase; // ME
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UINT16 MeLimit; //
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UINT16 GbeBase; // GbE
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UINT16 GbeLimit; //
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UINT16 PdrBase; // PDR
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UINT16 PdrLimit; //
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UINT16 Region5Base; // Reserved region
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UINT16 Region5Limit; //
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UINT16 Region6Base; // Reserved region
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UINT16 Region6Limit; //
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UINT16 Region7Base; // Reserved region
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UINT16 Region7Limit; //
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UINT16 EcBase; // EC
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UINT16 EcLimit; //
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UINT16 Region9Base; // Reserved region
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UINT16 Region9Limit; //
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} FLASH_DESCRIPTOR_REGION_SECTION;
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// Flash block erase sizes
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#define FLASH_BLOCK_ERASE_SIZE_4KB 0x0000
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#define FLASH_BLOCK_ERASE_SIZE_8KB 0x0001
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#define FLASH_BLOCK_ERASE_SIZE_64KB 0x000F
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// Master section
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION {
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UINT16 BiosId;
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@ -125,14 +137,30 @@ typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION {
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UINT8 GbeWrite;
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} FLASH_DESCRIPTOR_MASTER_SECTION;
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// Master section v2 (Skylake+)
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION_V2 {
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UINT32 : 8;
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UINT32 BiosRead : 12;
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UINT32 BiosWrite : 12;
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UINT32 : 8;
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UINT32 MeRead : 12;
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UINT32 MeWrite : 12;
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UINT32 : 8;
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UINT32 GbeRead : 12;
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UINT32 GbeWrite : 12;
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UINT32 : 32;
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UINT32 : 8;
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UINT32 EcRead : 12;
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UINT32 EcWrite : 12;
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} FLASH_DESCRIPTOR_MASTER_SECTION_V2;
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// Region access bits in master section
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#define FLASH_DESCRIPTOR_REGION_ACCESS_DESC 0x01
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#define FLASH_DESCRIPTOR_REGION_ACCESS_BIOS 0x02
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#define FLASH_DESCRIPTOR_REGION_ACCESS_ME 0x04
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#define FLASH_DESCRIPTOR_REGION_ACCESS_GBE 0x08
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#define FLASH_DESCRIPTOR_REGION_ACCESS_PDR 0x10
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//!TODO: Describe PCH and PROC straps sections, as well as ICC and DMI tables
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#define FLASH_DESCRIPTOR_REGION_ACCESS_EC 0x20
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// Base address of descriptor upper map
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#define FLASH_DESCRIPTOR_UPPER_MAP_BASE 0x0EFC
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@ -155,7 +183,7 @@ typedef struct _VSCC_TABLE_ENTRY {
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// Base address and size of OEM section
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#define FLASH_DESCRIPTOR_OEM_SECTION_BASE 0x0F00
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#define FLASH_DESCRIPTOR_OEM_SECTION_SIZE 0xFF
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#define FLASH_DESCRIPTOR_OEM_SECTION_SIZE 0x100
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// Restore previous packing rules
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#pragma pack(pop)
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@ -216,18 +216,19 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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const FLASH_DESCRIPTOR_MAP* descriptorMap = (const FLASH_DESCRIPTOR_MAP*)(descriptor + sizeof(FLASH_DESCRIPTOR_HEADER));
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const FLASH_DESCRIPTOR_UPPER_MAP* upperMap = (const FLASH_DESCRIPTOR_UPPER_MAP*)(descriptor + FLASH_DESCRIPTOR_UPPER_MAP_BASE);
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const FLASH_DESCRIPTOR_REGION_SECTION* regionSection = (const FLASH_DESCRIPTOR_REGION_SECTION*)calculateAddress8(descriptor, descriptorMap->RegionBase);
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const FLASH_DESCRIPTOR_MASTER_SECTION* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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const FLASH_DESCRIPTOR_COMPONENT_SECTION* componentSection = (const FLASH_DESCRIPTOR_COMPONENT_SECTION*)calculateAddress8(descriptor, descriptorMap->ComponentBase);
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// GbE region
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QByteArray gbe;
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UINT32 gbeBegin = 0;
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UINT32 gbeEnd = 0;
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if (regionSection->GbeLimit) {
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gbeBegin = calculateRegionOffset(regionSection->GbeBase);
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gbeEnd = calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
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gbe = intelImage.mid(gbeBegin, gbeEnd);
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gbeEnd += gbeBegin;
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// Check descriptor version by getting hardcoded value of FlashParameters.ReadClockFrequency
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UINT8 descriptorVersion = 0;
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if (componentSection->FlashParameters.ReadClockFrequency == FLASH_FREQUENCY_20MHZ) // Old descriptor
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descriptorVersion = 1;
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else if (componentSection->FlashParameters.ReadClockFrequency == FLASH_FREQUENCY_17MHZ) // Skylake+ descriptor
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descriptorVersion = 2;
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else {
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msg(tr("parseIntelImage: unknown descriptor version with ReadClockFrequency %1h").hexarg(componentSection->FlashParameters.ReadClockFrequency));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// ME region
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QByteArray me;
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UINT32 meBegin = 0;
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@ -238,16 +239,7 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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me = intelImage.mid(meBegin, meEnd);
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meEnd += meBegin;
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}
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// PDR region
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QByteArray pdr;
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UINT32 pdrBegin = 0;
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UINT32 pdrEnd = 0;
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if (regionSection->PdrLimit) {
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pdrBegin = calculateRegionOffset(regionSection->PdrBase);
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pdrEnd = calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
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pdr = intelImage.mid(pdrBegin, pdrEnd);
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pdrEnd += pdrBegin;
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}
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// BIOS region
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QByteArray bios;
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UINT32 biosBegin = 0;
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@ -273,7 +265,43 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// GbE region
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QByteArray gbe;
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UINT32 gbeBegin = 0;
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UINT32 gbeEnd = 0;
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if (regionSection->GbeLimit) {
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gbeBegin = calculateRegionOffset(regionSection->GbeBase);
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gbeEnd = calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
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gbe = intelImage.mid(gbeBegin, gbeEnd);
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gbeEnd += gbeBegin;
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}
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// PDR region
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QByteArray pdr;
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UINT32 pdrBegin = 0;
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UINT32 pdrEnd = 0;
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if (regionSection->PdrLimit) {
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pdrBegin = calculateRegionOffset(regionSection->PdrBase);
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pdrEnd = calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
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pdr = intelImage.mid(pdrBegin, pdrEnd);
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pdrEnd += pdrBegin;
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}
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// EC region
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QByteArray ec;
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UINT32 ecBegin = 0;
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UINT32 ecEnd = 0;
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if (descriptorVersion == 2) {
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if (regionSection->EcLimit) {
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pdrBegin = calculateRegionOffset(regionSection->EcBase);
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pdrEnd = calculateRegionSize(regionSection->EcBase, regionSection->EcLimit);
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pdr = intelImage.mid(ecBegin, ecEnd);
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ecEnd += ecBegin;
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}
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}
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// Check for intersections between regions
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// Descriptor
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if (hasIntersection(descriptorBegin, descriptorEnd, gbeBegin, gbeEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with GbE region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -290,6 +318,11 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(descriptorBegin, descriptorEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// GbE
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if (hasIntersection(gbeBegin, gbeEnd, meBegin, meEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with ME region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -302,6 +335,11 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(gbeBegin, gbeEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// ME
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if (hasIntersection(meBegin, meEnd, biosBegin, biosEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with BIOS region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -310,23 +348,36 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(meBegin, meEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// BIOS
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if (hasIntersection(biosBegin, biosEnd, pdrBegin, pdrEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(biosBegin, biosEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// PDR
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if (descriptorVersion == 2 && hasIntersection(pdrBegin, pdrEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, PDR region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// Region map is consistent
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// Intel image
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QString name = tr("Intel image");
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QString info = tr("Full size: %1h (%2)\nFlash chips: %3\nRegions: %4\nMasters: %5\nPCH straps: %6\nPROC straps: %7\nICC table entries: %8")
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QString info = tr("Full size: %1h (%2)\nFlash chips: %3\nRegions: %4\nMasters: %5\nPCH straps: %6\nPROC straps: %7")
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.hexarg(intelImage.size()).arg(intelImage.size())
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.arg(descriptorMap->NumberOfFlashChips + 1) //
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.arg(descriptorMap->NumberOfRegions + 1) // Zero-based numbers in storage
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.arg(descriptorMap->NumberOfMasters + 1) //
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.arg(descriptorMap->NumberOfPchStraps)
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.arg(descriptorMap->NumberOfProcStraps)
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.arg(descriptorMap->NumberOfIccTableEntries);
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.arg(descriptorMap->NumberOfProcStraps);
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// Construct parsing data
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pdata.fixed = TRUE;
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@ -363,8 +414,10 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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}
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// Region access settings
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if (descriptorVersion == 1) {
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const FLASH_DESCRIPTOR_MASTER_SECTION* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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info += tr("\nRegion access settings:");
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info += tr("\nBIOS:%1%2h ME:%3%4h GbE:%5%6h")
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info += tr("\nBIOS:%1h %2h ME:%3h %4h GbE:%5h %6h")
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.hexarg2(masterSection->BiosRead, 2)
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.hexarg2(masterSection->BiosWrite, 2)
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.hexarg2(masterSection->MeRead, 2)
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@ -388,6 +441,40 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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info += tr("\nPDR %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
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}
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else if (descriptorVersion == 2) {
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const FLASH_DESCRIPTOR_MASTER_SECTION_V2* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION_V2*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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info += tr("\nRegion access settings:");
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info += tr("\nBIOS: %1h %2h ME: %3h %4h\nGbE: %5h %6h EC: %7h %8h")
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.hexarg2(masterSection->BiosRead, 3)
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.hexarg2(masterSection->BiosWrite, 3)
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.hexarg2(masterSection->MeRead, 3)
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.hexarg2(masterSection->MeWrite, 3)
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.hexarg2(masterSection->GbeRead, 3)
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.hexarg2(masterSection->GbeWrite, 3)
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.hexarg2(masterSection->EcRead, 3)
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.hexarg2(masterSection->EcWrite, 3);
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// BIOS access table
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info += tr("\nBIOS access table:");
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info += tr("\n Read Write");
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info += tr("\nDesc %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ");
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info += tr("\nBIOS Yes Yes");
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info += tr("\nME %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ");
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info += tr("\nGbE %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ");
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info += tr("\nPDR %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
|
||||
info += tr("\nEC %1 %2")
|
||||
.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_EC ? "Yes " : "No ")
|
||||
.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_EC ? "Yes " : "No ");
|
||||
}
|
||||
|
||||
// VSCC table
|
||||
const VSCC_TABLE_ENTRY* vsccTableEntry = (const VSCC_TABLE_ENTRY*)(descriptor + ((UINT16)upperMap->VsccTableBase << 4));
|
||||
@ -430,6 +517,11 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
|
||||
QModelIndex pdrIndex;
|
||||
result = parsePdrRegion(pdr, pdrBegin, index, pdrIndex);
|
||||
}
|
||||
// Parse EC region
|
||||
else if (descriptorVersion == 2 && offsets.at(i) == ecBegin) {
|
||||
QModelIndex ecIndex;
|
||||
result = parseEcRegion(ec, ecBegin, index, ecIndex);
|
||||
}
|
||||
if (result)
|
||||
return result;
|
||||
}
|
||||
@ -445,6 +537,8 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
|
||||
IntelDataEnd = biosEnd;
|
||||
else if (LastRegionOffset == pdrBegin)
|
||||
IntelDataEnd = pdrEnd;
|
||||
else if (descriptorVersion == 2 && LastRegionOffset == ecBegin)
|
||||
IntelDataEnd = ecEnd;
|
||||
|
||||
if (IntelDataEnd > (UINT32)intelImage.size()) { // Image file is truncated
|
||||
msg(tr("parseIntelImage: image size %1 (%2) is smaller than the end of last region %3 (%4), may be damaged")
|
||||
@ -613,6 +707,31 @@ STATUS FfsParser::parsePdrRegion(const QByteArray & pdr, const UINT32 parentOffs
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
STATUS FfsParser::parseEcRegion(const QByteArray & ec, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index)
|
||||
{
|
||||
// Check sanity
|
||||
if (ec.isEmpty())
|
||||
return ERR_EMPTY_REGION;
|
||||
|
||||
// Get parent's parsing data
|
||||
PARSING_DATA pdata = parsingDataFromQModelIndex(parent);
|
||||
|
||||
// Get info
|
||||
QString name = tr("EC region");
|
||||
QString info = tr("Full size: %1h (%2)").
|
||||
hexarg(ec.size()).arg(ec.size());
|
||||
|
||||
// Construct parsing data
|
||||
pdata.fixed = TRUE;
|
||||
pdata.offset += parentOffset;
|
||||
if (pdata.isOnFlash) info.prepend(tr("Offset: %1h\n").hexarg(pdata.offset));
|
||||
|
||||
// Add tree item
|
||||
index = model->addItem(Types::Region, Subtypes::PdrRegion, name, QString(), info, QByteArray(), ec, parsingDataToQByteArray(pdata), parent);
|
||||
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
STATUS FfsParser::parseBiosRegion(const QByteArray & bios, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index)
|
||||
{
|
||||
// Sanity check
|
||||
|
||||
@ -66,6 +66,7 @@ private:
|
||||
STATUS parseMeRegion(const QByteArray & me, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index);
|
||||
STATUS parseBiosRegion(const QByteArray & bios, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index);
|
||||
STATUS parsePdrRegion(const QByteArray & pdr, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index);
|
||||
STATUS parseEcRegion(const QByteArray & ec, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index);
|
||||
|
||||
STATUS parsePadFileBody(const QModelIndex & index);
|
||||
STATUS parseSections(QByteArray sections, const QModelIndex & index);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user